What are the major differences between RISC-V and traditional RISC CPUs?
For those of you new to RISC-V, it is an open-source Instruction Set Architecture (ISA) that began as a 2010 project of UC Berkeley’s Parallel Computing Laboratory and is now ushering in a new era of chip design and innovation. As the adoption of RISC-V accelerates, it will be used to support a plethora of devices and products, from automotive to 5G and wireless networking, to data centers and beyond. We are seeing new RISC-V architectures that are, for example, designed to deliver new capabilities for pre-silicon development, allowing new ways for SoC (System-on-Chip) architects and system software developers to define new products. This enables organizations to quickly prototype a product, including products for automotive with safety packages. (an excerpt from “Driving the Future of Chip Innovation: Top Three Reasons to Adopt RISC-V” by Desi Banatao) As a RISC architecture, the RISC-V ISA is a load–store architecture . Its floating-point instructions use IEEE 754 floating-poi